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| CD4071BMS, CD4072BMS CD4075BMS December 1992 CMOS OR Gate Pinout CD4071BMS TOP VIEW Features * High-Voltage Types (20V Rating) * CD4071BMS Quad 2-Input OR Gate * CD4072BMS Dual 4-Input OR Gate * CD4075BMS Triple 3-Input OR Gate * Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Standardized Symmetrical Output Characteristics * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" A1 B2 J=A+B 3 K=C+C 4 C5 D6 VSS 7 14 VDD 13 H 12 G 11 M = G + H 10 L = E + F 9F 8E CD4072BMS TOP VIEW J=A+B+C+D 1 A2 B3 C4 14 VDD 13 K = E +F + G + H 12 H 11 G 10 F 9E 8 NC Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4071, CD4072 *H4H H1B H3W CD4075 Only H4Q D5 NC 6 VSS 7 NC = NO CONNECTION CD4075BMS TOP VIEW A1 B2 D3 E4 F5 K=D+E+F 6 VSS 7 14 VDD 13 G 12 H 11 I 10 L = G + H + I 9 J=A+B+C 8C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 File Number 3323 7-444 CD4071BMS, CD4072BMS, CD4075BMS Functional Diagram VDD 14 B A D C F E H G 1 2 5 6 8 9 12 13 3 4 J K L M 10 11 7 VSS CD4071BMS VDD 14 A B C D 2 3 4 5 1 J 9 E 10 F 11 G 12 H 7 VSS 13 K CD4072BMS VDD 14 C B A F E 1 2 8 3 4 6 K 9 J 5 D 11 I 12 H 13 G 7 VSS 10 L CD4075BMS 7-445 Specifications CD4071BMS, CD4072BMS, CD4075BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25o C +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 11 1.5 4 V V V V MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 0.5 50 0.5 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND +25oC, +125oC, -55oC 14.95 VOH > VOL < VDD/2 VDD/2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-446 Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 250 338 200 270 UNITS ns ns ns ns PARAMETER Propagation Delay SYMBOL TPHL TPLH TTHL TTLH CONDITIONS (NOTES 1, 2) VDD = 5V, VIN = VDD or GND Transition Time +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC oC o o o MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 7 - MAX 0.25 7.5 0.5 15 0.5 30 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -2.6 -2.4 -4.2 3 120 90 UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns +125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 Input Voltage Low Input Voltage High Propagation Delay VIL VIH TPHL TPLH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 7-447 Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time SYMBOL TTHL TTLH CIN CONDITIONS VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC o MIN - MAX 100 80 7.5 UNITS ns ns pF Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25oC +25oC +25oC +25oC +25oC o MIN -2.8 0.2 VOH > VDD/2 - MAX 2.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.1A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A 7-448 Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz PART NUMBER CD4071BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 3, 4, 10, 11 3, 4, 10, 11 3, 4, 10, 11 1, 2, 5 - 9, 12 - 13 7 7 7 14 1, 2, 5, 6, 8, 9, 12 - 14 14 1, 2, 5, 6, 8, 9, 12 - 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12, 13 PART NUMBER CD4072BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 1, 6, 8, 13 1, 6, 8, 13 6, 8 1, 6, 8, 13 2 - 5, 7, 9 - 12 7 7 7 14 2 - 5, 9 - 12, 14 14 2 - 5, 9 - 12, 14 1, 13 2 - 5, 9 - 12 PART NUMBER CD4075BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 6, 9, 10 6, 9, 10 6, 9, 10 1 - 5, 7, 8, 11 - 13 7 7 7 14 1 - 5, 8, 11 - 14 14 1 - 5, 8, 11 - 14 6, 9, 10 1 - 5, 8, 11 - 13 7-449 CD4071BMS, CD4072BMS, CD4075BMS VDD 14 p p p n n n n 3 (4, 10, 11) VDD p p * 1 (6, 8, 13) * 2 (5,9, 12) p n VSS n 7 VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES) B 1 (6, 8, 13) A 2 (5, 9, 12) J 3 (4, 10, 11) FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES) VDD INV.1** VDD p p p n p p n n n VSS VSS VDD p p VSS 1 (13) n n VDD p VDD * 2 (12) VSS * 3 (11) INV 2** * 5 (9) INV 3** n n VDD * 4 (10) INV 4** VSS VSS ** INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1. * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES) A 2 (12) B 3 (11) D 5 (9) C 4 (10) J 1 (13) FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES) 7-450 CD4071BMS, CD4072BMS, CD4075BMS VDD 14 p p p n p p p 9 (6, 10) * 8 (5, 13) n p n n n n * 2 (4, 12) n p VDD n * 1 (3, 11) n VSS * 7 VSS ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES) A 1 (3, 11) B 2 (4, 12) 9 (6, 10) C 8 (5, 13) J FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES) Typical Performance Characteristics PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 20 200 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 15 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT VOLTAGE (VO) (V) 150 SUPPLY VOLTAGE (VDD) = 5V 10 10V 100 5V 5 50 10V 15V 0 5 10 15 INPUT VOLTAGE (VIN) (V) 20 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 7-451 CD4071BMS, CD4072BMS, CD4075BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC (Continued) OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 104 -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS o FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 105 POWER DISSIPATION PER GATE (PD) (W) 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V AMBIENT TEMPERATURE (TA) = +25 C TRANSITION TIME (tTHL, tTLH) (ns) 104 8 6 4 200 SUPPLY VOLTAGE (VDD) = 5V 150 103 2 8 6 4 2 100 10V 50 15V 102 8 6 4 2 CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 0 0 10 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 1 103 10 102 INPUT FREQUENCY (fI) (kHz) FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONAS A FUNCTION OF FREQUENCY 7-452 CD4071BMS, CD4072BMS, CD4075BMS Chip Dimensions and Pad Layouts CD4071BMS CD4072BMS CD4075BMS Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kA - 14kA, AL. 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 453 |
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